[C.CC USERS] Modeling computer bits

[P.H.Welch]

Hi Matt,

Just reading mail for first time since Christmas, :).

Emulating digital electronics is a fun thing to do with occam - it was one
of the first exercises I tried back in 1984/85.

Martin wrote:
> I don't know if its relavent but I belive peter wrote a paper on modeling
> electonics in occam at some point. I don't think he covered ram though.

The paper is downloadable here:

  http://www.cs.kent.ac.uk/pubs/1989/246/

but the PDF was re-created a few years ago from troff sources - software
rot has damaged some of the diagrams slightly.  The key idea was to model
basic gates as IO-PAR devices, in a way that gives a one-cyle propagation
delay.  Arbitrary-cycle delays can be easily imposed by adding IO-PAR delay
components (that remember the last 'n' signals) in series with the basic
gate elements.  Gates can be glued together with broadcasting deltas,
which are IO-SEQ devices that impose zero-cycle delays (in the emulated
timings).  Clock and reset signals are (tediously) routed through like
this - I was not thinking 'barriers' then, interested now though!

Arbitrary digital circuits can be built like this and accurate timing
information obtained.  Examples in the paper are a simple latch (that
gives us a 1-bit memory), a JK flip-flop (with circuit taken from some
lost textbook), 4-bit counters and a fun test circuit.  The whole thing
scaled beautifuly with transputers.  A larger circuit than the one in
the paper was an early occam system with over 1M processes!  We could run
multiple tests in 32-way parallel, using separate bits of each INT word
for each test - all at the same speed as one test.

RAM should be straightforward ... except that you need to model a bus
and channels don't do that naturally ... as you found when you tried to
plug all your registers into the same channel array ends!  Maybe SHARED
channel ends are the answer?  Needs thought.

Anyway, that ancient (1987) paper is something to read and may spark ideas.

Hey, Happy New Year,

Peter.