[C.CC USERS] Modeling computer bits

[Matt Jadud]

On Fri, Dec 31, 2010 at 18:51, Martin Ellis <ellism88 at gmail.com> wrote:
> I think you may be able to model ram access using shared channel bundles.
> Not sure if this fits the model though.

Sadly, no. The challenge may come in the difference between HDL and
occam. However, it should be possible to make this work.

http://books.google.com/books?id=THie6tt-2z8C&lpg=PP1&ots=0Q4dhWLXUW&dq=Elements%20of%20Computer%20Systems%20book&pg=PA43#v=onepage&q=Elements%20of%20Computer%20Systems%20book&f=false

Around page 43 you'll find the section on sequential logic. RAM could
easily be modeled by some static arrays, but I'm interested in
actually trying to build up the pieces in occam. I'm not 100% sure
why, although I like the idea of being able to implement the software
for the course on the Arduino, so that students can then write a
compiler for the machine that they wrote (as opposed to it all being
in simulation).

First steps first, though, and I need to debug my register
implementation. Depending on where in a PAR I put my SYNC, I can force
different errors in my code. This, traditionally, has meant that
something is wrong with our implementation. Or, I am doing something
very wrong with BARRIERs. I'll continue poking, and may put this on
Github if others want to look and comment.

Cheers,
Matt