From P.H.Welch at kent.ac.uk Thu May 24 18:33:37 2018 From: P.H.Welch at kent.ac.uk (P.H.Welch) Date: Thu, 24 May 2018 18:33:37 +0100 Subject: [C.CC USERS] CPA 2018 - Keynote & Final Call for Papers Message-ID: ==================================================================== | | | Communicating Process Architectures (CPA) 2018 | | | | The 40th. WoTUG Conference on Concurrent and Parallel Systems | | | | Sunday (evening) 19th. - Wednesday (afternoon) 22nd. August 2018 | | | | http://wotug.cs.unlv.edu/cpa2018 E-mail: cpa2018 at wotug.org | | | | Host institute: Technische Universitat Dresden, Dresden, Germany | | | ==================================================================== This is the final Call for Papers for Communicating Process Architectures 2018, the 40th WoTUG conference on concurrent and parallel systems. CPA 2018 will be held at Technische Universitat Dresden and is hosted by the Faculty of Computer Science. It starts on the evening of Sunday 19th. August and finishes after lunch on Wednesday 22rd. August. Conference sessions will take place at the Faculty. <<< NEW IN THIS CALL >>> The timetable for submission and reviewing of papers has been revised: Paper submission: 15 June 2018 Notification of acceptance: 25 July 2018 Final revised CRC due: 1 August 2018 Author registration: 1 August 2018 Proceedings will be published by IOS Press after the conference, with all delegates receiving a copy. Electronic (PDF) copies of all papers will be available to delegates at the conference. <<< NEW IN THIS CALL >>> We are pleased to announce that Professor Christian Mayr will present a Keynote Address at CPA 2018 with the following Title and Abstract: "SpiNNaker-2: a 10 Million Core Processor System for Machine Learning and Brain Simulation" In the EU flagship HBP, TU Dresden and University of Manchester jointly develop the SpiNNaker-2 processor platform for brain simulation. Characteristics of the SpiNNaker-2 system are 144 ARM cores per chip (including various numerical accelerators), for overall 10 Mio cores with 5PFLOPS CPU performance and 0.6ExaOPS deep learning acceleration. The chips are implemented in a 22nm FDSOI technology, running as low as 0.4V with the usage of our Adaptive Body Biasing methodology. The SpiNNaker-2 system combines highly efficient machine learning, bio-inspired signal processing at millisecond latency and ultra-low energy operation. Thus, besides the main usage as a neuroscience platform, SpiNNaker-2 opens up completely new avenues in areas such as tactile internet, autonomous driving and industry 4.0. Prof. Dr.-Ing. habil. Christian Mayr is Chair of Highly-Parallel VLSI-Systems and Neuromorphic Circuits at Technische Universitat Dresden, (https://tu-dresden.de/ing/elektrotechnik/iee/hpsn). Themes for CPA 2018 ------------------- CPA is concerned with concurrency at all scales. It aims to bridge the gap between the mathematical theory of concurrency and its practical application to the design, implementation and validation of parallel applications for embedded, multicore and distributed computing systems. Areas of interest to the CPA community include, but are not limited to: * design and implementation of programming languages and environments for concurrent systems; * runtime environments for parallel and distributed applications; * design patterns and implementation techniques for concurrent software; * theoretical models for concurrency; * formal specification of concurrent systems and formal languages supporting these approaches; * modelling and model-driven development of concurrent software architectures; * verification and analysis of concurrent systems; * model-checking techniques and tools for development and analysis; * design and effective use of multicore/manycore processors and massively parallel computer architectures; * the teaching of concurrency at school, university and postgraduate level; * tools and languages for hardware-software co-design; * hardware and software approaches to reconfigurable computing; * concurrent applications within academia and industry, such as complex systems simulation, robotic control and high-performance engineering; * reports on experience with concurrency in an industrial context. Further Information ------------------- Details of how to submit papers, proposals for informal fringes, and proposals for mini-workshops can be found on the "Author", "Fringe" and "Workshop" pages respectively of the conference website (http://wotug.cs.unlv.edu/cpa2018). Just follow the links with those names. Accepted papers will be published in the CPA 2018 Proceedings by IOS Press (in their Concurrent Systems Engineering Series). All submissions will be refereed by an international panel of academic and industrial reviewers, with extensive feedback given to authors. Authors retain copyright on their papers, shared with the publishers. This means that authors have the right to reuse any material from these papers in future publications (e.g. in extended revisions for journals). CPA runs in a single track over two and a half days, with space for approximately 20 half-hour presentations and a number of 1 or 2 hour workshops. In addition, two evening Fringe sessions provide a forum for presenting and discussing new ideas and/or work in progress. The conference registration fee (covering admission to all sessions, one copy of the Proceedings, coffee/tea breaks, lunches and evening meals, including the conference dinner) will be announced on the "Registration" page shortly, which also gives details of a number of bursaries to support students attending the conference. Delegates are responsible for booking their own accommodation: a range of hotels will be listed on the "Location" page of the conference website. Thank you for reading this Call. If you have any questions about the conference, please email us at or contact one of us directly (see below for the organising committee). Finally, we would be grateful if you would forward this call to colleagues who might like to know about CPA 2018 and may not otherwise discover it. Many thanks and we look forward to seeing you in historic Dresden! Professor Dr. Rainer Spallek (Host) Chair of VLSI Design, Diagnostics and Architecture Faculty of Computer Science, Technische Universitat Dresden, Germany Dr.ir. Jan Broenink Associate Professor of Embedded Control Systems, University of Twente, The Netherlands Dr. Kevin Chalmers Senior Lecturer, School of Computing, Edinburgh Napier University, UK Professor Jan B??kgaard Pedersen Associate Professor, School of Computer Science, University of Nevada Las Vegas, USA Professor Brian Vinter Head of High Performance Computing, University of Copenhagen, Denmark Professor Peter Welch Emeritus Professor of Parallel Computing, University of Kent, UK